The present subject matter relates to semiconductor design technologies, particularly to an address strobe pulse generation circuit for a semiconductor memory device, and more particularly to a circuit capable of adjusting tRCD (RAS to CAS Delay) to be consistent with characteristics of test equipment during a test operation of the semiconductor memory.
In general semiconductor memory devices, particularly DRAM, there is a specific specification requiring that a delay time within a given range always has to be between an RAS (Row Address Strobe) signal generated in response to an active command ACT and a CAS (Column Address Strobe) signal created in response to a read command or write command. This delay time is called tRCD, which has been used by those skilled in the art.
FIG. 1 is a block diagram showing a conventional address strobe pulse generation circuit for a semiconductor memory device.
Referring to FIG. 1, the conventional address strobe pulse generation circuit for the semiconductor memory device includes an RAS pulse generator 140 for generating an RAS pulse RAS in response to an active command signal ACT and a clock pulse CLK_P, and a CAS pulse generator 100 for generating a CAS pulse CAS in response to a column command signal RD and the clock pulse CLK_P. In addition, it further includes a clock pulse generator 180 for generating the clock pulse CLK_P having the same frequency as a clock signal CLK and a preset activation interval in response to the clock signal CLK.
More specifically, the RAS pulse generator 140 is provided with an active pulse generator 150 for latching the active command signal ACT and the clock pulse CLK_P to generate an active pulse ACT_P, and an RAS pulse output unit 160 for outputting the active pulse ACT_P as the RAS pulse RAS in response to a power-up signal PWRUP.
The CAS pulse generator 100 is provided with a column pulse generator 110 for latching the column command signal RD and the clock pulse CLK_P to produce a column pulse RD_P, and a CAS pulse output unit 120 for providing the column pulse RD_P as the CAS pulse CAS in response to the power-up signal PWRUP.
The column command signal RD set forth above is a signal which is inputted in all operations where a column address is used in DRAM. That is, the abbreviation “RD” shown in the drawing denotes a read command, and a write command WR may also be contained in the column command signal.
FIG. 2 is a detailed circuit diagram of the CAS pulse output unit of the conventional address strobe pulse generation circuit shown in FIG. 1.
Referring to FIG. 2, the CAS pulse output unit 120 included in the conventional address strobe pulse generation circuit is provided with a driver 122 for driving an output node OUT_NODE in response to a column pulse RD_P received through an input end IN, and a pulse output unit 124 for providing a pulse applied to the output node OUT_NODE as a CAS pulse CAS in response to an inverted signal PWRUPB of a power-up signal.
Here, the driver 122 is composed of a PMOS transistor P1 and an NMOS transistor N1 between a power supply voltage VDD end and a ground voltage VSS end. Among these, the PMOS transistor P1 controls the connection of the power supply voltage VDD end and the output node OUT_NODE in response to the column pulse RD_P received via a gate coupled to the input end IN, and the NMOS transistor N1 controls the connection of the output node OUT_NODE and the ground voltage VSS end in response to the column pulse RD_P accepted via a gate coupled to the input end IN.
Further, the pulse output unit 124 is composed of a first inverter INV1 for taking and inverting a pulse applied to the output node OUT_NODE, a NAND gate NAND for performing a NAND-operation on an output signal of the first inverter INV1 and an inverted signal PWRUPB of the power-up signal to provide a resulting signal to the output node OUT_NODE, a second inverter INV2 for accepting and inverting an output signal of the first inverter INV1, and a third inverter INV3 for inverting an output signal of the second inverter INV2 to output an resulting signal as the CAS pulse CAS through an output end OUT.
Although not shown, the RAS pulse output unit 160 is similar to the CAS pulse output unit 120 in configuration. One difference therebetween is that the column pulse RD_P is inputted to the input end IN and the CAS pulse CAS is outputted from the output end OUT in the CAS pulse output unit 120, while the active pulse ACT_P is inputted to the input IN end and the RAS pulse RAS is outputted from the output OUT end in the RAS pulse output unit 160.
Based on the configuration as above, the operation of the conventional address strobe pulse generation circuit for the semiconductor memory device will be described below in detail.
First, the clock pulse generator 180 serves to prevent malfunctions of the semiconductor memory device due to a variation of activation interval of the clock signal CLK caused by the effect of environments under which the semiconductor memory device operates, which will occur because the clock signal CLK inputted thereto is a signal from the outside of the semiconductor memory device.
That is to say, in response to activation of the clock signal CLK being inputted, the clock pulse generator 180 provides the clock pulse CLK_P which is deactivated after it is activated for a given time period.
The CAS pulse generator 100 generates the CAS pulse CAS in response to the column command signal RD, wherein the CAS pulse CAS is controlled to have the same activation interval as the clock pulse CLK_P.
Further, the CAS pulse generator 100 is configured such that the operation thereof is controlled in response to the power-up signal PWRUP. This is to prevent the generation of a wrong CAS pulse CAS before the power-up signal PWRUP is activated.
The RAS pulse generator 140 generates the RAS pulse RAS in response to the active command signal ACT. At this time, the RAS pulse RAS is controlled to have the same activation interval as the clock pulse CLK_P.
Also, the RAS pulse generator 140 is configured such that the operation thereof is controlled in response to the power-up signal PWRUP. This is to prevent the generation of wrong RAS pulse RAS before the power-up signal PWRUP is activated.
The conventional address strobe pulse generation circuit for the semiconductor memory device having the configuration and operation set forth above employs a method which makes the time points of inputting the active command signal ACT and the column command signal RD different from each other in order to meet the specification of tRCD.
Thus, the following operational timing diagrams can be shown, on the basis of the conventional address strobe pulse generation circuit for the semiconductor memory device.
FIG. 3A is a signal timing diagram showing an operation of the conventional address strobe pulse generation circuit depicted in FIG. 1.
Referring to FIG. 3A, the conventional address strobe pulse generation circuit for the semiconductor memory device operates in the sequence as follows.
First of all, the clock pulse CLK_P is outputted in response to the clock signal CLK ({circle around (1)}). Next, the active command signal ACT is inputted in response to the active command Active ({circle around (2)}). The active command signal ACT and the clock pulse CLK_P are latched to generate the active pulse ACT_P ({circle around (3)}). Thereafter, the RAS pulse RAS is outputted in response to the active pulse ACT_P.
After inputting the active command signal ACT in response to the active command Active, the column command signal RD is inputted in response to the read command Read after a preset tRCD delay time, which corresponds to one period of the clock signal CLK in the drawing, regardless of the output process of the RAS pulse RAS ({circle around (5)}).
The column command signal RD and the clock pulse CLK_P are latched to output a column pulse RD_P ({circle around (6)}). Next, the CAS pulse CAS is provided in response to the column pulse RD_P.
As shown in FIG. 3A, in the conventional address strobe pulse generation circuit for the semiconductor memory device, the time taken between the active command signal ACT and the column command signal RD being inputted was just tRCD of DRAM.
Meanwhile, as the capacity of the DRAM increases, the development of DRAM that applies an address double pump that is a technique of effectively addressing a plurality of memory cells therein has been started.
Briefly explaining the address double pump, the number of address pins should be increased in proportion to the increase in the capacity of DRAM. At this time, only preset address pins are shared and used, rather than indefinitely increasing the number of address pins.
For example, if the number of address pins required in DRAM is 12 (A0 to A11), only preset 6 pins (A0 to A5) are used, rather than all of 12 pins, wherein 6 bits address are received twice in order to receive the entire address of 12 bits.
By the way, the DRAM using such an address double pump gives rise to a phenomenon in which the minimum delay value of tRCD is limited, as set forth below.
FIG. 3B is a signal timing diagram showing an operation of the conventional address strobe pulse generation circuit applied to a semiconductor memory device using the address double pump.
Referring to FIG. 3B, it can be seen that timing variations ({circle around (1)}˜{circle around (7)}) of signals and pulses ACT, ACT_P, RD, RD_P, RAS, and CAS, used when the conventional address strobe pulse generation circuit depicted in FIG. 1 is applied to a semiconductor memory device using the address double pump, are completely identical to those used in the conventional address strobe pulse generation circuit of FIG. 3A.
However, the read command signal RD cannot be inputted at next clock just after input of the active command signal ACT in FIG. 3B, whereas the read command signal RD is inputted at a next clock just after input of the active command signal ACT in FIG. 3A.
This is because the row address inputted in response to the active command signal ACT is not ended until the next clock after input of the active command signal ACT due to the operation of the address double pump.
Thus, there is a phenomenon in which the minimum delay time of tRCD corresponds to two clocks in the case of DRAM that uses the address double pump, while the minimum delay time of tRCD corresponds to one clock in DRAM that does not use the address double pump.
In case where the DRAM that uses the address double pump operates in normal mode, although the minimum value of tRCD is limited, this may lead to a variation in the specification of DRAM only, but becomes no factor causing malfunctions.
However, in actually manufacturing DRAM through a series of processes, DRAM manufactured in wafer level has to be tested to know whether it meets the tRCD value required in the preset specification.
In addition, in order to keep the probability such that the DRAM that has passed such test malfunctions during an actual operation minimized, the test is generally conducted by applying severer environments or conditions than those in the place where DRAM is actually used.
This test method is also applied to testing tRCD of DRAM. Assuming that the specification of tRCD delay time of DRAM is 15 ns, the test is done under the criterion of tRCD delay time of about 10 to 12 ns less than the value given in the specification. In this case, if DRAM has a higher tRCD delay time than the above criterion, it is decided to be fail.
Thus, when testing DRAM to check whether it has a tRCD value meeting the preset specification during the process of manufacturing DRAM using the address double pump, if the DRAM is under the state that it is already set to the minimum tRCD delay time, the normal test cannot be conducted as not being done within any time less than the minimum tRCD delay time.
Due to this, the design change needs to be made in order to carry out the test, thereby requiring a prolonged time period in developing DRAM using the address double pump.